A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. Each pixel cell has a charge storage region, formed on or in the substrate, which is connected to the gate of an output transistor that is part of a readout circuit. The charge storage region may be constructed as a floating diffusion region. In some imager circuits, each pixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state before the transfer of charge to it; (4) transfer of charge to the storage region accompanied by charge amplification; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
CMOS imagers of the type discussed above are generally known as discussed, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524 and U.S. Pat. No. 6,333,205, assigned to Micron Technology, Inc., which are hereby incorporated by reference in their entirety.
A typical four transistor (4T) CMOS imager pixel 10 is shown in FIG. 1. The pixel 10 includes a photosensor 12 (e.g., photodiode, photogate, etc.), transfer transistor 14, floating diffusion region FD, reset transistor 16, source follower transistor 18 and row select transistor 20. The photosensor 12 is connected to the floating diffusion region FD by the transfer transistor 14 when the transfer transistor 14 is activated by a transfer gate control signal TX.
The reset transistor 16 is connected between the floating diffusion region FD and an array pixel supply voltage Vaa_pix. A reset control signal RST is used to activate the reset transistor 16, which resets the floating diffusion region FD to the array pixel supply voltage Vaa_pix level as is known in the art.
The source follower transistor 18 has its gate connected to the floating diffusion region FD and is connected between the array pixel supply voltage Vaa_pix and the row select transistor 20. The source follower transistor 18 converts the charge stored at the floating diffusion region FD into an electrical output voltage signal Vout. The row select transistor 20 is controllable by a row select signal SEL for selectively connecting the source follower transistor 18 and its output voltage signal Vout to a column line 22 of a pixel array.
The signals output from the pixel 10 are analog voltages. The output signals must be converted from analog to digital for further processing. Thus, the pixel output signals are usually sent to an analog-to-digital converter (ADC) (not shown in FIG. 1). Many CMOS image sensors use a ramp analog-to-digital converter, which is essentially a comparator and associated control logic. In the conventional ramp analog-to-digital converter, an input voltage of the signal to be converted is compared with a gradually increasing reference voltage. The gradually increasing reference voltage is generated by a digital-to-analog converter (DAC) as it sequences through and converts digital codes into analog voltages. This gradually increasing reference voltage is known as the ramp voltage. In operation, when the ramp voltage reaches the value of the input voltage, the comparator generates a signal that latches the digital code of the DAC. The latched digital code is used as the output of the analog-to-digital converter.
Ramp analog-to-digital converters are typically made up of very simple circuits, which results in low power consumption. The problem with ramp analog-to-digital converters is that they must step through, one value at a time, all possible digital values that could be generated and output by the analog-to-digital converter. The typical implementation of a ramp generator for a single slope ramp analog-to-digital converter contains 2N ramp unit cells. FIG. 2 illustrates a portion of a ramp generator 40 for a 12-bit ramp analog-to-digital converter. The ramp generator 40 contains 4096 unit cells 421, 422, . . . , 424096 (collectively referred to herein as “unit cells 42”) having their outputs connected to a capacitor 44 to output a ramp output voltage RAMP OUTPUT. The unit cells 42 are connected in series to form a long shift register.
When the analog-to-digital conversion starts, a logic ‘1’ is loaded into the first unit cell 421. At the next clock edge, the logic ‘1’ in the first unit cell 421 is shifted to the second unit cell 422 while the first unit cell is loaded with a logic ‘1’ once again. At this point, two of the 4096 unit cells 42 are loaded with a logic ‘1’ while the others cells all logic ‘0’ (presuming for example that the initial condition of all the unit cells 42 is to be loaded with a logic ‘0’). Meanwhile, the outputs OUT_1, OUT_2, . . . , OUT_4096 of the cells 42 are applied to the capacitor 44 to form the ramp output RAMP OUT. This operation continues until all 4096 unit cells are loaded with ‘1’. Thus, the ramp generation process requires 4096 clock cycles (i.e., 2N cycles) to complete the analog-to-digital conversion.
FIG. 3 illustrates a typical ramp unit cell 42i used in the generator 40 of FIG. 2. The unit cell 42i includes a D flip-flop 50, two transistors 52, 56 and a capacitor 54. The input of the flip-flop 50 receives a shifted input bit Si. The output Q of the flip-flop 50 is connected to the gates of the transistors 52, 56 and is also passed to the next cell (not shown) as a shifted output So. The terminals of the first transistor 52 are connected between a high reference voltage Vref_hi and the capacitor 54. The terminals of the second transistor 56 are connected between a low reference voltage Vref_lo and the capacitor 54.
In operation, for each clock cycle CLK, an output voltage OUT_i is generated from the cell 42i. As shown in FIG. 2, each output OUT_i is combined at the capacitor 44 to form the ramp output RAMP OUT.
In principle, the number of ramp operation cycles NRAMP can be expressed as NRAMP=2N, where N is the data resolution of the imager (or analog-to-digital converter) in number of bits. For example, if an imager has a 12-bit resolution, then a 12-bit ramp analog-to-digital converter must be used to obtain the correct digital output. For 12-bit ramp analog-to-digital converters there may be 4,096 steps in any single conversion cycle to ensure that the input voltage is converted to the appropriate digital code (one of 4,096 possibilities). Likewise, for a 10-bit ramp analog-to-digital converter, there may be 1,024 steps in any single conversion cycle. Presuming, for example, that the comparator operating frequency is 100 MHz, the conversion takes approximately 1/100 kHz and 1/25 kHz for 10-bit and 12-bit resolutions, respectively. These are long conversion periods, which increase by a factor of two for every additional bit of resolution in the sensor (or the analog-to-digital converter).
Since it is desirable to increase the resolution of CMOS image sensors, it is desirable to decrease the number of steps in the analog-to-digital conversion cycle. Accordingly, there is a desire and need for an analog-to-digital converter that substantially decreases the analog-to-digital conversion time in an imager that uses ramp analog-to-digital converters.
In addition, it is known that most natural signals have quantum fluctuation. For example, for an average number of incident photons Nphoton, there is a fluctuation with a deviation of approximately √{square root over (Nphoton)}, such that the corresponding signal-to-noise ratio (S/N) is limited to:S/N=Nphoton/√{square root over (Nphoton)}=√{square root over (Nphoton)}.  (1)
This type of noise is often referred to as “shot noise” and occurs in most charge detection devices such as e.g., imager pixels. For an average number of integrated electrons Nele in a pixel there should be a shot noise component of √{square root over (Nele)}. This means that the bits in an analog-to-digital conversion output that are below the level of √{square root over (Nele)} are not really meaningful. Thus, there is a need and desire to incorporate shot noise into the analog-to-digital conversion process used in today's imagers to increase the accuracy and speed of the conversion.